AND-gate clock

ABSTRACT

An AND-gate clock having an input stage, an output stage, and an isolation stage. The input stage receives two signals, and gates them to produce a high signal. The output stage is used to drive a load typically having a large load capacitance when both signals are true. The isolation stage isolates the input stage from the output stage when only one signal is true, therefore preventing power dissipation by current flow through the output driver stage. The isolation stage provides an alternative current path through smaller transistors, thereby incurring lesser power dissipation and requiring less layout area. A small driver stage may then be used.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to metal oxide semiconductor technology and in particular to AND-gate clocks.

2. Description of the Prior Art

The AND-ing of two or more inputs in a dynamic MOS clock circuit has been a particularly difficult problem, primarily because of the large transistor sizes involved and the high power dissipated before the clock is triggered. Previously, signals were ANDed in a dynamic clock as shown in FIG. 1. In this circuit the transistors T₁₀ and T₁₁ form an output stage wherein T₁₀ is the driving transistor. In this circuit, the output φ₃ is conditional upon both φ₁ and φ₂ being high. The problems occur when φ₁ occurs earlier than φ₂, since the node N₅ goes high while the Node N₂ remains high. In order to prevent φ₃ from rising during this time, transistor T₁₁ is typically much larger than the transistor T₁₀. However, the driving transistor, T₁₀, must be very large in order to handle the capacitance C_(L). Thus, T₁₁ becomes very large, as much as approximately 700 microns in channel length for T₁₀ =100 microns. Also, during the time that φ₂ remains low, a large amount of current flows through T₁₀ and T₁₁.

SUMMARY OF THE INVENTION

The present invention allows φ₁ to occur earlier than φ₂. However, in this circuit, the gate of T₁₀ remains low, holding T₁₀ off. The additional power dissipated during this time is only the current flowing through an additional depletion transistor and a drain transistor. This can be kept small, since the capacitive load on the gate of T₁₀ is only that associated with the driving transistor T₁₀, typically a small fraction of C_(L). Also, the transistor T₁₁ can now be made equal or even smaller than T₁₀, since T₁₀ is now turned off. Finally, when the second output does go high, a full bootstrap voltage will appear on the input to the driving transistor, since the drain transistor will be turned off and the gate of the depletion transistor will be at the supply voltage. Therefore, considerable savings in power dissipation and layout area are achieved.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior art AND-gate clock;

FIG. 2 is a schematic diagram of one embodiment of the invention; and

FIG. 3 is a clock diagram for use in connection with the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 2, a preferred embodiment of the invention, an AND-gate clock, is generally indicated by reference numeral 10. The AND-gate clock 10 is generally made up of stages shown by the broken blocks 12, 14 and 16. Block 12 includes an input stage, Block 14 includes an isolation stage, and Block 16 includes an output stage.

Looking to the input stage 12, a first transistor T₁ is shown with its source grounded and its gate tied to a precharge signal. A second transistor, T₂, has its source connected to the drain of the transistor T₁, forming a node 1, N₁. The transistor T₂ receives a first signal, φ₁, at its gate, and a second signal, φ₂, at its drain. A third transistor, T₃, has its source grounded and its gate tied to the node, N₁. The drain of the transistor T₃ is tied to the source of a transistor, T₄, forming a node N₂. The gate of the transistor T₄ is tied to a precharge signal while the drain is connected to a supply voltage, V_(cc). A fifth transistor, T₅, has its source tied to the node N₂ and its gate connected to the supply voltage V_(cc). The drain of the transistor T₅ is tied to the gate of a sixth transistor, T₆. The sixth transistor, T₆, has its drain tied to the input first signal, φ₁. A seventh transistor, T₇, has its source grounded and its gate tied to the node N₂. The drain of T₇ is connected to the source of an eighth transistor, T₈, whose gate is tied to the source of T₆. The drain of the eighth transistor, T₈, is tied to supply voltage V_(cc) . Finally, a capacitance C₁ is connected between the source of the transistor T₈ at the node N₄ and the gate of the transistor T₈ at node N₅.

The isolation stage 14 includes two transistors, T₉ and D₁. D₁ is a depletion transistor. The transistor T₉ has its source connected to the node N₄ and its gate connected to the node N₂. The drain of the transistor T₉ is tied to node N₆ to which the source of the transistor D₁ is also tied. The drain of the transistor D₁ is tied to the node N₅ and its gate is tied to the node N₄.

The output stage is a driver circuit composed of transistors T₁₀ and T₁₁. T₁₀ is a driver transistor with its gate connected to the node N₆ and its drain connected to supply voltage V_(cc). The source of the transistor T₁₀ is tied to a node N₇ which forms an output φ₃. The transistor T₁₁ has its source grounded and its gate connected to the node N₂. The drain of the transistor T₁₁ is connected to the node N₇. A load capacitance is represented by the capacitor C_(L) connected at the output N₇.

The operation of the AND-gate clock 10 may now be observed by referring to the timing diagram of FIG. 3. During precharge, φ₁ and φ₂ will be at zero volts and the precharge signal will be at a voltage level, typically V_(cc). In this manner the transistor T₁ is turned on while T₂ is off, bringing the node N₁ to zero volts. This turns off the transistor T₃ while the transistor T₄ has been turned on by a precharge signal, bringing node N₂ to V_(cc) -V_(T), where V_(T) is the threshold voltage. Transistor T₅ is similarly turned on by the supply voltage V_(cc), which brings the node N₃ to V_(cc) -V_(T). In this manner, transistor T₆ is turned on, but the source and drain will be at zero volts because of φ₁. The voltage at N₂ turns on the transistor T₇, bringing N₄ to ground. As N₄ and N₅ are now at zero volts, the transistor T₈ is off.

Because of the voltage at N₂, the transistor T₉ is turned on, bringing the node N₆ to ground. Remembering that a transistor is on whenever V_(G) -V_(S) -V_(T) is greater than 0, and that a depletion transistor has a negative threshold voltage, the zero volts at N₄ will still turn on the transistor D₁. Because of the small difference between V_(G) and V_(S), depletion transistor D₁ will operate somewhat as a resistance.

Transistor T₁₀ will be turned off by the zero voltage at its gate while the transistor T₁₁ is turned on by the voltage level at N₂, thereby taking the node N₇ to ground. Therefore, at this point, φ₃ is at zero output while both input signals are at zero input.

If φ₁ and φ₂ occur simultaneously, the circuit operates as a clock circuit and the invention serves to produce an output at φ₃. However, φ₁ and φ₂ do not always occur simultaneously, and, in many applications, φ₂ may well occur after φ₁. Note that one objective here is to keep φ₃ low until both φ₁ and φ₂ are high.

Referring to the prior art circuit in FIG. 1, if φ₁ occurs earlier than φ₂, N₅ will be driven high while N₂ will remain high. A large current flow then occurs through transistors T₁₀ and T₁₁, which can only be compensated for by making transistor T₁₁ much larger than transistor T₁₀. This is typically seven times as large. However, the transistor T₁₀ must be very large in order to drive the load capacitance. Therefore, transistor T₁₁ is larger than desirable.

Under the invention disclosed here, if only φ₁ goes high, while in the meantime φ_(p) has gone to a zero stage, transistor T₁ is turned off while transistor T₂ is turned on. However, node N₁ remains at zero volts because of the input at φ₂. Therefore, T₃ remains off, while T₄ has similarly turned off. N₂ will remain floating at about V_(cc) -V_(T) while N₃, due to the inherent capacitance C_(i) across the gate and drain of T₆, will float up due to the rise of φ₁. Thus, a full signal φ₁ is transmitted across the transistor T₆.

It should be noted that the node N₄ has remained at ground and the full signal at N₅ will now charge the capacitors C₁. Transistor T₈ has turned on, which will then raise the node N₄ to a point between V_(cc) and ground due to the current flow between T₈ and T₇. This rise in voltage at N₄ will raise the node N₅ even higher because of a bootstrap effect and will maintain D₁ in an on state. The transistor D₁ and the transistor T₉ are ratioed to give approximately zero volts at N₆. This is done by making T₉ larger than D₁. In a typical case, the channel W₁ of D₁ might be 8 microns, causing the channel of T₉ to be approximately 56 microns. Finally, T₁₀ is maintained off by the low voltage at N₆, and T₁₁ remains on, keeping N₇ at zero.

Now as φ₂ rises to its voltage level, T₂ is turned on, bringing N₁ to a full V_(cc) -V_(T), and turning on T₃, bringing N₂ to zero volts. N₃ will now be brought toward zero volts, turning off T₆, although N₅ maintains its charge due to C₁. T₇ is now turned off as is T₁₁, which brings N₄ to V_(cc) -V_(T). This turns on the transistor D₁ hard with a full transmission of the charged N₅ to the node N₆, which turns on the transistor T₁₀. Because of the bootstrap effect at N₅ and N₆, the node N₇ will receive a full V_(cc). φ₃ now is an output at a V_(cc) level.

In summary, the upper path through the transistor T₆ has offered a faster path than the lower path through transistors T₂, T₃. While the prior art allowed a current flow through transistors T₁₀ and T₁₁, the AND-gate clock 10 provides an alternative current flow through D₁ and T₉. In this manner, T₁₁ does not have to be made significantly larger than T₁₁, as T₉ and D₁ have accomplished this purpose. 

What is claimed is:
 1. An AND-gate clock comprising:an input stage adapted to receive a first and a second input signal for providing a plurality of interstage signals in response to the first and second input signals; an output stage for driving a load having a large capacitance; and an isolation stage means coupled between the input stage and the output stage for receiving the plurality of interstage signals and for enabling the output stage to provide a true level to the load only when the first and second input signals are at a true level.
 2. The AND-gate clock of claim 1 wherein the isolation stage means provides a current path in alternative to current flow through the output stage when the second input signal is at a false level.
 3. The AND-gate clock of claim 1 wherein the input stage comprises:a first MOSFET having its source grounded and its gate connected to a precharge signal; a second MOSFET having its source connected to the drain of the first MOSFET, its gate connected to a first input, and its drain connected to a second input; a third MOSFET having its gate connected to the drain of the first MOSFET and its source grounded; a fourth MOSFET having its source connected to the drain of the third MOSFET, its gage connected to a precharge signal, and its drain connected to a supply voltage; a fifth MOSFET having its source connected to the drain of the third MOSFET and its gate connected to a supply voltage; a sixth MOSFET having its drain connected to the first input and its gate connected to the drain of the fifth MOSFET; a seventh MOSFET having its source grounded and its gate connected to the drain of the third MOSFET; an eighth MOSFET having its source connected to the drain of the seventh MOSFET, its gate connected to the source of the sixth MOSFET, and its drain connected to a supply voltage; a capacitance connected between the gate and source of the eighth MOSFET.
 4. The AND-gate clock of claim 3 wherein the isolation stage comprises:a ninth MOSFET having its source connected to the drain of the seventh MOSFET and its gate connected to the drain of the third MOSFET; and a depletion channel MOSFET having its drain connected to the source of the sixth MOSFET, its gate connected to the drain of the seventh MOSFET, and its source connected to the drain of the ninth MOSFET.
 5. The AND-gate clock of claim 1 wherein the output stage comprises:a first MOSFET having its gate coupled to the isolation stage means and its drain connected to a supply voltage; and a second MOSFET having its source grounded, its gate coupled to the input stage, and its drain connected to the source of the first MOSFET whereby an output capable of driving a large load capacitance is produced at the source of the first MOSFET when the first and second input signals are high.
 6. The AND-gate clock of claim 1 wherein the input stage has three outputs and the isolation stage means comprises:a first MOSFET having its gate connected to a first output of the input stage and its source connected to a second output of the input stage; and a depletion channel MOSFET having its drain connected to a third output of the input stage, its gate connected to the source of the first MOSFET and its source connected to the drain of the first MOSFET.
 7. A circuit for driving a large load capacitance when two input signals are high comprising:a first input node; a second input node; circuit means for turning on a first MOSFET when the second input node is low and for turning the first MOSFET off when both the first input node and the second input node are high; a driver stage for producing a high level output when the first MOSFET is turned off; and an isolation stage coupled between the circuit means and the driver stage and containing a depletion channel MOSFET responsive to the first MOSFET for causing the driver stage to produce a high level output when the first MOSFET is turned off.
 8. The AND-gate clock of claim 7 wherein the isolation stage provides a current path to divert current from the output stage when the first signal is high and the second signal is low.
 9. An AND-gate clock comprising:a first MOSFET having its source grounded and its gate connected to a precharge signal; a second MOSFET having its source connected to the drain of the first MOSFET, its gate connected to a first input, and its drain connected to a second input; a third MOSFET having its gate connected to the drain of the first MOSFET and its source grounded; a fourth MOSFET having its source connected to the drain of the third MOSFET, its gage connected to a precharge signal, and its drain connected to a supply voltage; a fifth MOSFET having its source connected to the drain of the third MOSFET and its gate connected to a supply voltage; a sixth MOSFET having its drain connected to the first input and its gate connected to the drain of the fifth MOSFET; a seventh MOSFET having its source grounded and its gate connected to the drain of the third MOSFET; an eighth MOSFET having its source connected to the drain of the seventh MOSFET, its gate connected to the source of the sixth MOSFET, and its drain connected to a supply voltage; a capacitance connected between the gate and source of the eighth MOSFET; a ninth MOSFET having its source connected to the drain of the seventh MOSFET and its gate connected to the drain of the third MOSFET; a depletion channel MOSFET having its drain connected to the source of the sixth MOSFET and its gate connected to the drain of the seventh MOSFET; a tenth MOSFET having its gate connected to the source of the depletion MOSFET and its drain connected to a supply voltage; and an eleventh MOSFET having its source grounded, its gate connected to the drain of the third MOSFET, and its drain connected to the source of the tenth MOSFET whereby an output capable of driving a large load capacitance is produced at the source of the tenth MOSFET when the first and second inputs are high. 